Library { Name "Lib_VSMRAC" Version 2.09 PaperOrientation landscape PaperType usletter PaperUnits inches BlockDefaults { Orientation right ForegroundColor black BackgroundColor white DropShadow off NamePlacement normal FontName "Helvetica" FontSize 10 FontWeight normal FontAngle normal ShowName on } AnnotationDefaults { HorizontalAlignment center VerticalAlignment middle ForegroundColor black BackgroundColor white DropShadow off FontName "Helvetica" FontSize 10 FontWeight normal FontAngle normal } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight normal FontAngle normal } System { Name "Lib_VSMRAC" Location [87, 248, 567, 688] Open on ScreenColor white Block { BlockType SubSystem Name "Euclidean\nNorm" Ports [1, 1, 0, 0, 0] Position [285, 75, 315, 105] ShowPortLabels on System { Name "Euclidean\nNorm" Location [623, 417, 978, 562] Open off ScreenColor white Block { BlockType Inport Name "x" Position [35, 50, 55, 70] Port "1" PortWidth "-1" SampleTime "-1" } Block { BlockType Math Name "sqrt(x.x)" Ports [1, 1, 0, 0, 0] Position [215, 55, 245, 85] Operator sqrt } Block { BlockType Reference Name "x.x" Ports [2, 1, 0, 0, 0] Position [115, 52, 145, 83] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Outport Name "||x||" Position [295, 60, 315, 80] Port "1" OutputWhenDisabled held InitialOutput "0" } Line { SrcBlock "x" SrcPort 1 Points [15, 0] Branch { DstBlock "x.x" DstPort 1 } Branch { Points [0, 15] DstBlock "x.x" DstPort 2 } } Line { SrcBlock "x.x" SrcPort 1 DstBlock "sqrt(x.x)" DstPort 1 } Line { SrcBlock "sqrt(x.x)" SrcPort 1 DstBlock "||x||" DstPort 1 } } } Block { BlockType SubSystem Name "Last VS Lead Filter\nUnit Vector Control" Ports [2, 1, 0, 0, 0] Position [265, 180, 360, 240] ShowPortLabels on System { Name "Last VS Lead Filter\nUnit Vector Control" Location [174, 38, 843, 573] Open off ScreenColor white Block { BlockType Inport Name "UN-1" Position [55, 45, 75, 65] Port "1" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "wfN-1" Position [55, 380, 75, 400] Port "2" PortWidth "-1" SampleTime "-1" } Block { BlockType StateSpace Name "I/Fi(s)" Position [140, 37, 200, 73] A "AF" B "BF" C "CF" D "DF" X0 "x0F" } Block { BlockType StateSpace Name "I/Li(s)" Position [410, 192, 470, 228] Orientation left A "ALi" B "BLi" C "CLi" D "DLi" X0 "x0Li" } Block { BlockType StateSpace Name "LFwfi-1" Position [145, 372, 205, 408] A "ALFwfi" B "BLFwfi" C "CLFwfi" D "DLFwfi" X0 "x0LFwfi" } Block { BlockType Sum Name "ei" Ports [2, 1, 0, 0, 0] Position [290, 47, 320, 78] Inputs "+-" } Block { BlockType Reference Name "ei.ei" Ports [2, 1, 0, 0, 0] Position [360, 102, 390, 133] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Constant Name "epsiloni" Position [330, 314, 385, 336] Value "epsiloni" } Block { BlockType Sum Name "rhoi" Ports [2, 1, 0, 0, 0] Position [465, 316, 495, 349] Inputs "++" } Block { BlockType Product Name "rhoi.ei/||ei||" Ports [3, 1, 0, 0, 0] Position [525, 57, 555, 103] Inputs "*/*" } Block { BlockType Reference Name "wfi.wfi" Ports [2, 1, 0, 0, 0] Position [275, 437, 305, 468] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Math Name "||ei||" Ports [1, 1, 0, 0, 0] Position [445, 105, 475, 135] Operator sqrt } Block { BlockType Math Name "||wfi||" Ports [1, 1, 0, 0, 0] Position [360, 440, 390, 470] Operator sqrt } Block { BlockType Outport Name "UN" Position [605, 70, 625, 90] Port "1" OutputWhenDisabled held InitialOutput "0" } Line { SrcBlock "LFwfi-1" SrcPort 1 Points [45, 0; 0, 55] Branch { Points [0, 15] DstBlock "wfi.wfi" DstPort 2 } Branch { DstBlock "wfi.wfi" DstPort 1 } } Line { SrcBlock "rhoi" SrcPort 1 Points [10, 0] DstBlock "rhoi.ei/||ei||" DstPort 3 } Line { SrcBlock "epsiloni" SrcPort 1 DstBlock "rhoi" DstPort 1 } Line { SrcBlock "||wfi||" SrcPort 1 Points [40, 0; 0, -115] DstBlock "rhoi" DstPort 2 } Line { SrcBlock "wfi.wfi" SrcPort 1 DstBlock "||wfi||" DstPort 1 } Line { SrcBlock "wfN-1" SrcPort 1 DstBlock "LFwfi-1" DstPort 1 } Line { SrcBlock "rhoi.ei/||ei||" SrcPort 1 Points [15, 0] Branch { Points [0, 130] DstBlock "I/Li(s)" DstPort 1 } Branch { DstBlock "UN" DstPort 1 } } Line { SrcBlock "I/Li(s)" SrcPort 1 Points [-150, 0; 0, -140] DstBlock "ei" DstPort 2 } Line { SrcBlock "ei" SrcPort 1 Points [15, 0] Branch { Points [0, 45] Branch { Points [0, 15] DstBlock "ei.ei" DstPort 2 } Branch { DstBlock "ei.ei" DstPort 1 } } Branch { DstBlock "rhoi.ei/||ei||" DstPort 1 } } Line { SrcBlock "I/Fi(s)" SrcPort 1 DstBlock "ei" DstPort 1 } Line { SrcBlock "UN-1" SrcPort 1 DstBlock "I/Fi(s)" DstPort 1 } Line { SrcBlock "ei.ei" SrcPort 1 DstBlock "||ei||" DstPort 1 } Line { SrcBlock "||ei||" SrcPort 1 Points [15, 0; 0, -40] DstBlock "rhoi.ei/||ei||" DstPort 2 } } } Block { BlockType SubSystem Name "Regressor\nVector" Ports [3, 1, 0, 0, 0] Position [95, 302, 150, 358] ShowPortLabels on System { Name "Regressor\nVector" Location [500, 609, 864, 865] Open off ScreenColor white Block { BlockType Inport Name "u" Position [45, 50, 65, 70] Port "1" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "y" Position [45, 120, 65, 140] Port "2" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "r" Position [45, 205, 65, 225] Port "3" PortWidth "-1" SampleTime "-1" } Block { BlockType Mux Name "Mux" Ports [4, 1, 0, 0, 0] Position [250, 106, 285, 169] Inputs "4" } Block { BlockType StateSpace Name "w1" Position [120, 42, 180, 78] A "ALambda" B "BLambda" C "CLambda" D "DLambda" X0 "x0Lambda" } Block { BlockType StateSpace Name "w2" Position [120, 112, 180, 148] A "ALambda" B "BLambda" C "CLambda" D "DLambda" X0 "x0Lambda" } Block { BlockType Outport Name "w" Position [315, 130, 335, 150] Port "1" OutputWhenDisabled held InitialOutput "0" } Line { SrcBlock "u" SrcPort 1 DstBlock "w1" DstPort 1 } Line { SrcBlock "w1" SrcPort 1 Points [45, 0; 0, 55] DstBlock "Mux" DstPort 1 } Line { SrcBlock "w2" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "w" DstPort 1 } Line { SrcBlock "y" SrcPort 1 Points [15, 0] Branch { DstBlock "w2" DstPort 1 } Branch { Points [0, 55; 125, 0; 0, -40] DstBlock "Mux" DstPort 3 } } Line { SrcBlock "r" SrcPort 1 Points [155, 0; 0, -55] DstBlock "Mux" DstPort 4 } } } Block { BlockType SubSystem Name "Unit vector\ncontrol" Ports [2, 1, 0, 0, 0] Position [80, 178, 170, 242] ShowPortLabels on System { Name "Unit vector\ncontrol" Location [198, 308, 703, 513] Open off ScreenColor white Block { BlockType Inport Name "x" Position [65, 40, 85, 60] Port "1" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "rho" Position [65, 140, 85, 160] Port "2" PortWidth "1" SampleTime "-1" } Block { BlockType Product Name "rho.x/||x||" Ports [3, 1, 0, 0, 0] Position [325, 43, 355, 87] Inputs "*/*" } Block { BlockType Reference Name "x.x" Ports [2, 1, 0, 0, 0] Position [160, 82, 190, 113] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Math Name "||x||" Ports [1, 1, 0, 0, 0] Position [245, 85, 275, 115] Operator sqrt } Block { BlockType Outport Name "rho x/||x||" Position [410, 55, 430, 75] Port "1" OutputWhenDisabled held InitialOutput "0" } Line { SrcBlock "rho" SrcPort 1 Points [220, 0] DstBlock "rho.x/||x||" DstPort 3 } Line { SrcBlock "rho.x/||x||" SrcPort 1 DstBlock "rho x/||x||" DstPort 1 } Line { SrcBlock "x" SrcPort 1 Points [45, 0] Branch { Points [0, 40] Branch { Points [0, 15] DstBlock "x.x" DstPort 2 } Branch { DstBlock "x.x" DstPort 1 } } Branch { DstBlock "rho.x/||x||" DstPort 1 } } Line { SrcBlock "x.x" SrcPort 1 DstBlock "||x||" DstPort 1 } Line { SrcBlock "||x||" SrcPort 1 Points [15, 0; 0, -35] DstBlock "rho.x/||x||" DstPort 2 } } } Block { BlockType SubSystem Name "VS Lead Filter\nUnit Vector Control" Ports [3, 3, 0, 0, 0] Position [70, 61, 175, 119] ShowPortLabels on System { Name "VS Lead Filter\nUnit Vector Control" Location [355, 33, 1015, 688] Open off ScreenColor white Block { BlockType Inport Name "Ui-1" Position [35, 30, 55, 50] Port "1" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "wfi-1" Position [35, 365, 55, 385] Port "2" PortWidth "-1" SampleTime "-1" } Block { BlockType Inport Name "Unfi-1" Position [40, 520, 60, 540] Port "3" PortWidth "-1" SampleTime "-1" } Block { BlockType StateSpace Name "I/Fi(s)" Position [120, 22, 180, 58] A "AF" B "BF" C "CF" D "DF" X0 "x0F" } Block { BlockType StateSpace Name "I/Li(s)" Position [390, 177, 450, 213] Orientation left A "ALi" B "BLi" C "CLi" D "DLi" X0 "x0Li" } Block { BlockType StateSpace Name "LFUnfi-1" Position [125, 512, 185, 548] A "ALFUnfi" B "BLFUnfi" C "CLFUnfi" D "DLFUnfi" X0 "x0LFUnfi" } Block { BlockType StateSpace Name "LFwfi-1" Position [125, 357, 185, 393] A "ALFwfi" B "BLFwfi" C "CLFwfi" D "DLFwfi" X0 "x0LFwfi" } Block { BlockType Reference Name "Unfi.Unfi1" Ports [2, 1, 0, 0, 0] Position [255, 577, 285, 608] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Sum Name "ei" Ports [2, 1, 0, 0, 0] Position [270, 32, 300, 63] Inputs "+-" } Block { BlockType Reference Name "ei.ei" Ports [2, 1, 0, 0, 0] Position [340, 87, 370, 118] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Constant Name "epsiloni" Position [310, 294, 365, 316] Value "epsiloni" } Block { BlockType Sum Name "rhoi" Ports [3, 1, 0, 0, 0] Position [445, 299, 475, 331] Inputs "+++" } Block { BlockType Product Name "rhoi.ei/||ei||" Ports [3, 1, 0, 0, 0] Position [505, 42, 535, 88] Inputs "*/*" } Block { BlockType Reference Name "wfi.wfi" Ports [2, 1, 0, 0, 0] Position [255, 422, 285, 453] SourceBlock "simulink/Linear/Dot Product" SourceType "Dot Product" } Block { BlockType Math Name "||Unfi||" Ports [1, 1, 0, 0, 0] Position [345, 580, 375, 610] Operator sqrt } Block { BlockType Math Name "||ei||" Ports [1, 1, 0, 0, 0] Position [425, 90, 455, 120] Operator sqrt } Block { BlockType Math Name "||wfi||" Ports [1, 1, 0, 0, 0] Position [340, 425, 370, 455] Operator sqrt } Block { BlockType Outport Name "Ui" Position [585, 55, 605, 75] Port "1" OutputWhenDisabled held InitialOutput "0" } Block { BlockType Outport Name "wfi" Position [585, 365, 605, 385] Port "2" OutputWhenDisabled held InitialOutput "0" } Block { BlockType Outport Name "Unfi" Position [585, 520, 605, 540] Port "3" OutputWhenDisabled held InitialOutput "0" } Line { SrcBlock "rhoi" SrcPort 1 Points [10, 0] DstBlock "rhoi.ei/||ei||" DstPort 3 } Line { SrcBlock "epsiloni" SrcPort 1 DstBlock "rhoi" DstPort 1 } Line { SrcBlock "||Unfi||" SrcPort 1 Points [50, 0] DstBlock "rhoi" DstPort 3 } Line { SrcBlock "||wfi||" SrcPort 1 Points [40, 0; 0, -125] DstBlock "rhoi" DstPort 2 } Line { SrcBlock "LFUnfi-1" SrcPort 1 Points [45, 0] Branch { Points [0, 55] Branch { Points [0, 15] DstBlock "Unfi.Unfi1" DstPort 2 } Branch { DstBlock "Unfi.Unfi1" DstPort 1 } } Branch { DstBlock "Unfi" DstPort 1 } } Line { SrcBlock "Unfi.Unfi1" SrcPort 1 DstBlock "||Unfi||" DstPort 1 } Line { SrcBlock "LFwfi-1" SrcPort 1 Points [45, 0] Branch { Points [0, 55] Branch { Points [0, 15] DstBlock "wfi.wfi" DstPort 2 } Branch { DstBlock "wfi.wfi" DstPort 1 } } Branch { DstBlock "wfi" DstPort 1 } } Line { SrcBlock "wfi.wfi" SrcPort 1 DstBlock "||wfi||" DstPort 1 } Line { SrcBlock "Unfi-1" SrcPort 1 DstBlock "LFUnfi-1" DstPort 1 } Line { SrcBlock "wfi-1" SrcPort 1 DstBlock "LFwfi-1" DstPort 1 } Line { SrcBlock "rhoi.ei/||ei||" SrcPort 1 Points [15, 0] Branch { Points [0, 130] DstBlock "I/Li(s)" DstPort 1 } Branch { DstBlock "Ui" DstPort 1 } } Line { SrcBlock "I/Li(s)" SrcPort 1 Points [-150, 0; 0, -140] DstBlock "ei" DstPort 2 } Line { SrcBlock "ei" SrcPort 1 Points [15, 0] Branch { Points [0, 45] Branch { Points [0, 15] DstBlock "ei.ei" DstPort 2 } Branch { DstBlock "ei.ei" DstPort 1 } } Branch { DstBlock "rhoi.ei/||ei||" DstPort 1 } } Line { SrcBlock "I/Fi(s)" SrcPort 1 DstBlock "ei" DstPort 1 } Line { SrcBlock "Ui-1" SrcPort 1 DstBlock "I/Fi(s)" DstPort 1 } Line { SrcBlock "ei.ei" SrcPort 1 DstBlock "||ei||" DstPort 1 } Line { SrcBlock "||ei||" SrcPort 1 Points [15, 0; 0, -40] DstBlock "rhoi.ei/||ei||" DstPort 2 } } } } }